`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:58:54 03/18/2014 
// Design Name: 
// Module Name:    CLK_div 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module CLK_div(output reg CLK_out,
	input CLK);
	
	reg [1:0] counter = 0;
	always@(posedge CLK) begin
		counter <= counter +1'b1;
		CLK_out <= counter[1];
	end
endmodule
